`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/29 12:49:24
// Design Name: 
// Module Name: 2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module float_mutiple_tb(
    
    );

     reg aclk=0;
     reg s_axis_a_tvalid;
     reg [31 : 0] s_axis_a_tdata;
     reg  s_axis_b_tvalid;
     reg [31 : 0] s_axis_b_tdata;
     wire m_axis_result_tvalid;
     reg m_axis_result_tready;
     wire [31 : 0] m_axis_result_tdata;





ip_mutiple your_instance_name (
  .aclk(aclk),                                  // input wire aclk
  .s_axis_a_tvalid(s_axis_a_tvalid),            // input wire s_axis_a_tvalid
  .s_axis_a_tdata(s_axis_a_tdata),              // input wire [31 : 0] s_axis_a_tdata
  .s_axis_b_tvalid(s_axis_b_tvalid),            // input wire s_axis_b_tvalid
  .s_axis_b_tdata(s_axis_b_tdata),              // input wire [31 : 0] s_axis_b_tdata
  .m_axis_result_tvalid(m_axis_result_tvalid),  // output wire m_axis_result_tvalid
  .m_axis_result_tready(m_axis_result_tready),  // input wire m_axis_result_tready
  .m_axis_result_tdata(m_axis_result_tdata)    // output wire [31 : 0] m_axis_result_tdata
);

always #5 aclk<=~aclk;

initial begin


  s_axis_a_tvalid<=1'b1;
  s_axis_a_tdata<=32'b01000000011111110010101100000010;
  s_axis_b_tvalid<=1'b1;
  s_axis_b_tdata<=32'b01000000100001100111111011111010;
  m_axis_result_tready=1;
  end



  endmodule